To make the binary counter more versatile, we need to be able to start the count sequence with any number rather than zero. Simulation trace for the 4-bit binary up-down counter.Ĩ.5.3 Binary Up-Down Counter with Parallel Load VHDL code for a 4-bit binary up-down counter. The two resulting equations areĬ out = D' a c in + D a' c in = (D a ) c in s = D' (a c in ) + D (a c in ) = a c inįigure 18. When we borrow, we get a 2, and 2 – 1 = 1, so s is also a 1. For example, for 0 – 1, we need to borrow, so c out is a 1. s is the difference of the subtraction and c out is a 1 if we need to borrow. For the bottom half, we are performing a subtraction of a The top half of the table is exactly the same as the HA truth table. Asserting D (setting to 1) will count down. The D signal is to select whether we want to count up or down. The half adder/subtractor (HAS) truth table is shown in Figure 16 (a). We can design an n-bit binary up-down counter just like the up counter except that we need both an adder and a subtractor for the data input to the register.
Simulation trace for the 4-bit binary up counter. VARIABLE value: INTEGER RANGE 0 TO 15 BEGINĮLSIF (Clock'EVENT AND Clock='1') THEN IF Count = '1' THENįigure 14. The VHDL code for the 4-bit binary up counter is shown in Figure 14 and the simulation trace in Figure 15.ĪRCHITECTURE Behavioral OF counter IS BEGIN
A 4-bit binary up counter with asynchronous clear: (a) circuit (b) truth table (c) logic symbol.
